Glass substrates are attracting increasing attention for advanced semiconductor packaging as AI accelerators, high-bandwidth memory (HBM), chiplets and heterogeneous integration push package dimensions and interconnect densities higher.
Compared with conventional organic substrates, glass offers several attractive properties, including high dimensional stability, low electrical loss, excellent surface flatness and the ability to tailor the coefficient of thermal expansion (CTE).
Through-glass vias, commonly known as TGVs, can also provide dense vertical electrical connections through the glass core.
These characteristics make glass a promising platform for large AI and high-performance computing packages, particularly as advanced packages become larger and incorporate more chiplets and HBM stacks. Recent industry analysis notes that some AI package architectures are already pushing package dimensions beyond approximately 70–100 mm per side, increasing concern about warpage and dimensional stability.
However, glass introduces its own manufacturing challenge:
It is brittle.
A glass substrate may appear perfectly flat and clean while still containing microscopic surface or edge damage. Under mechanical loading, metallization, lamination or thermal cycling, these small defects can become starting points for crack propagation.
For glass-core substrates, therefore, microcrack control is not a secondary cosmetic issue.
It can determine whether a substrate survives TGV processing, redistribution-layer fabrication, assembly, thermal cycling and long-term operation.
Why Microcracks Matter in Semiconductor Glass Substrates
The theoretical strength of glass can be extremely high, but practical strength is usually controlled by flaws.
Small scratches, chips and microcracks create stress concentration at their tips.
When tensile stress reaches a critical level, an initially microscopic crack can grow.
This distinction is extremely important in semiconductor packaging.
A substrate does not need to break during incoming inspection to be defective.
Instead, a small crack introduced during:
TGV formation,
grinding,
edge finishing,
dicing,
handling,
metallization,
or lamination
may remain stable during initial inspection and later propagate during package assembly or thermal cycling.
Recent glass-core research continues to identify surface and edge microcracks as important limitations for reliable package manufacturing.
This means glass substrate qualification needs to consider not only dimensional parameters but also the mechanical history of the material.
AI Packaging Makes Glass Reliability More Important
AI processors are driving increasingly complex package architectures.
A high-performance AI package may integrate:
a large logic die,
multiple chiplets,
several HBM stacks,
high-density redistribution layers,
power-delivery structures,
and very large substrate areas.
As package dimensions increase, controlling warpage becomes more difficult.
At the same time, smaller interconnect pitch requires increasingly accurate alignment.
A substrate that changes shape during processing can therefore create problems in lithography, bonding, solder-joint formation and chiplet placement.
Glass is attractive precisely because of its dimensional stability.
But the same stiff, brittle behavior that improves dimensional control can also make the material less tolerant of local stress concentrations.
The challenge is therefore not simply:
“Can glass reduce package warpage?”
The real engineering question is:
“Can glass maintain its dimensional advantages without generating cracks during fabrication and thermal cycling?”
1. TGV Drilling Is One of the First Critical Processes
Through-glass vias are essential for many glass-interposer and glass-core substrate architectures.
They provide vertical electrical connections between the two sides of the substrate.
TGVs can be produced using several techniques, including laser-based processes, laser-induced modification followed by etching, photosensitive-glass processing and other specialized methods.
Each method produces a different via profile and different levels of mechanical damage.
The objective is not simply to create a hole.
A production-quality TGV process must control:
via diameter,
via pitch,
taper,
sidewall roughness,
entrance and exit geometry,
microcracks,
debris,
and metallization compatibility.
Recent reviews of high-performance glass packaging identify TGV formation and microcrack control as tightly linked manufacturing challenges.
How TGV Formation Can Create Microcracks
Glass responds differently to machining than ductile materials such as copper or aluminum.
Localized thermal or mechanical energy can create small cracks around the via entrance, via exit or sidewall.
Possible damage includes:
radial cracks,
circumferential cracks,
small chips,
subsurface damage,
rough sidewalls,
and localized thermal modification.
These defects may initially be too small to produce immediate breakage.
However, once copper is deposited into the TGV and the substrate experiences later thermal cycles, local stress around the via can increase significantly.
This can turn a manufacturing defect into a reliability defect.
For this reason, TGV quality should not be evaluated using diameter and pitch alone.
The condition of the surrounding glass is equally important.
2. Via Diameter and Pitch Influence Mechanical Reliability
AI packaging requires increasing interconnect density.
One obvious way to increase density is to use smaller TGVs with tighter pitch.
Electrically, this can be attractive.
Mechanically, however, via geometry changes the local stress field.
The glass surrounding each via must carry stresses generated by both the metal filling and the surrounding package layers.
As TGV density increases, stress fields around neighboring vias can also interact.
A design that performs well with isolated vias may behave differently in a dense array.
Important TGV parameters therefore include:
via diameter,
via depth,
aspect ratio,
via-to-via pitch,
distance from the substrate edge,
and metal filling structure.
These parameters should be considered together rather than optimized independently.
3. Copper-Filled TGVs Create CTE-Mismatch Stress
Copper is widely used for TGV metallization because of its high electrical conductivity and compatibility with semiconductor interconnect processes.
However, copper and glass expand differently when temperature changes.
This creates thermo-mechanical stress at the Cu-glass interface.
A 2026 study of TGV structures showed that cooling from process temperatures can produce strong local stress near Cu-glass interfaces, with the surrounding glass experiencing high tensile stresses that may increase cracking risk.
The direction of stress also changes depending on the thermal history.
During heating, copper tends to expand differently from the surrounding glass.
During cooling, the situation reverses.
Repeated temperature cycling therefore subjects the interface to changing stress conditions.
Possible failure mechanisms include:
glass cracking,
Cu-glass delamination,
copper protrusion,
interfacial damage,
and void-related reliability problems.
Research published in 2026 specifically examined thermally induced TGV cracks and their impact on both mechanical and electrical behavior, emphasizing that CTE mismatch is a central reliability issue for Cu-filled TGV structures.
4. Thermal Cycling Can Turn Small Defects Into Large Cracks
A semiconductor package experiences multiple temperature changes before it ever reaches the final customer.
These can occur during:
dielectric curing,
metallization,
solder reflow,
bonding,
molding,
testing,
and reliability qualification.
During actual operation, AI processors also experience repeated heating and cooling as computational load changes.
A small glass defect may therefore experience thousands of stress cycles over the lifetime of the package.
This is why initial crack size matters.
A substrate may survive one thermal cycle and still fail after repeated cycling.
For glass-core substrates, reliability qualification should therefore evaluate crack propagation rather than simply asking whether cracks are visible before assembly.
5. Edge Quality Is Often Underestimated
TGVs are not the only location where cracks begin.
The substrate edge is another critical region.
Glass panels and wafers must eventually be cut, diced or separated into the required dimensions.
These operations can introduce:
edge chips,
microcracks,
surface scratches,
roughness,
and subsurface damage.
An edge may appear acceptable under low-magnification inspection while still containing a sharp microscopic flaw.
Because stress concentrates at crack tips, these defects can later propagate inward.
Recent glass-substrate studies have highlighted diced-edge microcracks as a potential starting point for fracture during subsequent thermal and mechanical loading.
For this reason, the edge specification should be treated as a functional reliability parameter.
What Should Be Controlled at the Glass Edge?
Important parameters can include:
edge chipping,
maximum defect size,
edge roughness,
corner quality,
edge profile,
surface-to-edge transition,
and crack-free inspection criteria.
The required limits will depend on substrate thickness, glass composition, panel size and downstream process.
Thin and large-format glass generally requires especially careful edge handling.
The substrate supplier and packaging manufacturer should also agree on whether edge inspection refers to visible chips only or includes microscopic crack detection.
6. Edge Clearance Matters When RDL Is Added
Redistribution layers create additional stress in glass packaging.
Copper traces and polymer dielectric layers have thermal and mechanical properties different from those of the glass core.
If an RDL structure extends too close to an existing edge flaw, package stress can increase the driving force for crack propagation.
Research on ultra-thin glass substrates has shown that RDL design, dielectric properties, glass thickness and edge clearance can substantially influence edge-crack behavior.
This means substrate design and package layout cannot be optimized independently.
A mechanically robust glass package requires co-design between:
glass material,
glass thickness,
edge quality,
RDL stack,
copper density,
dielectric material,
and edge clearance.
7. Warpage Remains Critical Even When Glass Is Used
One reason glass is attractive for AI packaging is its potential to provide better dimensional stability than organic substrate systems.
However, using glass does not eliminate warpage.
The complete package contains multiple materials:
glass,
copper,
polymer dielectrics,
silicon dies,
underfill,
molding compounds,
solder,
and sometimes additional reinforcement structures.
Each material has its own coefficient of thermal expansion and elastic modulus.
When the package temperature changes, these materials do not expand equally.
The resulting stress can cause the complete structure to bend.
Recent comparative packaging research emphasizes that glass-package warpage depends strongly on the surrounding stack architecture and the mechanical properties of molding, reinforcement and dielectric layers.
Therefore, low-CTE glass alone does not guarantee a flat finished package.
Bow, Warp and Local Deformation Are Different Problems
For substrate qualification, it is useful to distinguish several geometric issues.
Bow describes overall substrate curvature.
Warp represents the total out-of-plane deformation across the substrate.
Local deformation describes smaller-scale shape changes around features such as TGVs, metal layers or bonded dies.
A glass substrate may have excellent incoming flatness but develop substantial deformation after Cu plating or dielectric lamination.
This is why geometry should ideally be measured at multiple stages rather than only at incoming inspection.
8. Glass Thickness Influences Both Warpage and Crack Risk
Thinner glass can help reduce package thickness and may support certain advanced integration architectures.
However, thinner substrates are generally more mechanically sensitive.
As glass becomes thinner:
handling becomes more difficult,
edge defects become more significant,
substrate deflection increases,
and stresses from RDL and copper structures can have a stronger influence.
This creates an important engineering trade-off.
The thinnest glass is not necessarily the best glass.
The correct thickness depends on:
package size,
TGV density,
RDL design,
handling method,
temporary carrier strategy,
and reliability requirements.
Large AI packages may require different mechanical optimization from small RF or sensor packages.
9. Glass Composition and CTE Need to Match the Package Architecture
“Glass substrate” does not describe a single material.
Different glass compositions can provide different:
CTE,
Young’s modulus,
dielectric constant,
loss tangent,
chemical durability,
thermal stability,
and mechanical behavior.
For semiconductor packaging, CTE selection is especially important.
A glass composition can potentially be selected to better match silicon or the complete package architecture.
However, minimizing one CTE mismatch does not automatically eliminate all stresses.
A package may contain several materials with competing thermal expansion behavior.
Glass selection should therefore be based on the complete stack rather than one interface alone.
10. Surface Quality Also Influences Crack Strength
Surface scratches are another potential crack-initiation source.
This is particularly relevant after processes such as:
grinding,
lapping,
cleaning,
temporary bonding,
debonding,
and automated handling.
Contact with particles can also scratch the surface.
For optical components, a small scratch may mainly be considered an appearance or optical-quality problem.
For semiconductor packaging glass, the same scratch can become a mechanical reliability problem.
Surface inspection should therefore focus not only on cosmetic quality but also on defects capable of creating stress concentration.
11. Handling Becomes More Difficult as Glass Panels Become Larger
Advanced packaging is increasingly interested in larger substrates and panel-level processing.
Scaling from wafer-sized glass to large panels may improve manufacturing economics.
But it also creates new mechanical challenges.
A large thin glass panel can experience:
greater gravitational deflection,
higher handling stress,
larger thermal gradients,
and more opportunity for edge damage.
Robot contact areas, vacuum chucks, carriers, cassettes and transport systems therefore need to be designed specifically for glass.
A process that is safe for silicon wafers cannot automatically be assumed to be safe for large glass substrates.
12. Inspection Should Look for Defects Before They Become Failures
Traditional visual inspection is not sufficient for advanced glass substrates.
Many dangerous flaws can be microscopic.
Depending on the substrate and process, inspection may involve combinations of:
automated optical inspection,
high-magnification microscopy,
surface profilometry,
infrared inspection,
confocal measurement,
acoustic techniques,
and specialized crack-detection methods.
The objective is not simply to count defects.
Engineers need to understand:
where the defects occur,
their dimensions,
their orientation,
their relationship to TGVs,
and their distance from substrate edges and critical package structures.
A defect map can therefore provide much more useful information than a simple pass/fail statement.
13. TGV Inspection Should Include More Than Hole Diameter
For production glass substrates, TGV inspection can include:
via diameter,
via pitch,
position accuracy,
taper angle,
sidewall quality,
entrance chipping,
exit chipping,
microcrack condition,
metal filling,
voids,
and interfacial quality.
If the via is copper-filled, electrical continuity alone is not enough.
A via may initially conduct electricity while already containing mechanical damage that creates long-term reliability risk.
Electrical inspection and mechanical inspection should therefore complement each other.
14. Warpage Mapping Should Be Performed Across Temperature When Necessary
Room-temperature flatness measurements are useful, but they do not show the complete package behavior.
For advanced packaging development, temperature-dependent warpage analysis may provide more useful information.
The substrate or package can deform differently during:
heating,
peak processing temperature,
cooling,
and room-temperature recovery.
Understanding this deformation behavior helps engineers optimize:
glass composition,
substrate thickness,
RDL architecture,
copper balance,
dielectric selection,
and package symmetry.
For large AI packages, this can directly influence bonding and assembly yield.
15. What Buyers Should Specify When Sourcing Glass Substrates
An RFQ for semiconductor glass substrates should go beyond:
“Need 300mm glass wafer.”
A more useful specification should define the intended application and critical parameters.
Basic Substrate Parameters
Buyers should normally define:
glass type or required material properties,
diameter or panel dimensions,
thickness,
thickness tolerance,
TTV,
bow,
warp,
surface roughness,
and edge condition.
TGV Parameters
If TGV processing is required, the specification should include:
TGV diameter,
pitch,
aspect ratio,
taper,
position tolerance,
via density,
sidewall requirement,
entrance and exit quality,
metallization requirement,
and accepted crack criteria.
Reliability-Related Parameters
Depending on the project, the customer may also define:
edge chipping limit,
microcrack inspection,
thermal-cycle requirement,
warpage after processing,
Cu-glass interface reliability,
and required inspection reports.
Example Glass Substrate RFQ Structure
| Category | Parameter | Why It Matters |
|---|---|---|
| Material | Glass composition / type | Determines CTE, dielectric and mechanical behavior |
| Dimension | Wafer or panel size | Defines equipment compatibility |
| Geometry | Thickness | Influences rigidity and package height |
| Geometry | TTV | Affects process uniformity |
| Geometry | Bow / Warp | Influences lithography and assembly |
| Surface | Roughness | Important for RDL and bonding |
| Edge | Chip / crack limits | Controls fracture risk |
| TGV | Via diameter | Determines interconnect density |
| TGV | Via pitch | Affects routing density and stress interaction |
| TGV | Aspect ratio | Influences drilling and metallization |
| TGV | Sidewall quality | Influences plating and reliability |
| TGV | Entrance / exit chipping | Identifies drilling damage |
| Metallization | Cu fill quality | Influences electrical and mechanical reliability |
| Reliability | Thermal cycling | Evaluates stress-driven failure |
| Inspection | Crack detection method | Defines quality-control capability |
| Documentation | Wafer / panel mapping | Supports process and yield correlation |
The exact acceptance limits should be determined according to the package architecture rather than copied from unrelated applications.
16. Glass Substrate Qualification Should Follow the Manufacturing Flow
Incoming substrate inspection alone cannot fully predict final reliability.
A better qualification program follows the material through several critical manufacturing steps.
For example:
Bare glass inspection
↓
TGV formation
↓
TGV inspection
↓
Metallization
↓
RDL fabrication
↓
Dicing
↓
Assembly
↓
Thermal cycling
↓
Final crack and warpage inspection
This approach makes it easier to identify the exact process that introduces damage.
Without intermediate inspection, a crack discovered after final testing may be difficult to trace back to TGV drilling, dicing, lamination or another earlier operation.
17. Microcrack Control Is a Supply-Chain Issue
Microcrack reduction cannot be achieved by the glass manufacturer alone.
Multiple companies may participate in a glass-packaging supply chain:
glass material supplier,
substrate processor,
TGV manufacturer,
metallization provider,
RDL manufacturer,
OSAT,
and device company.
A substrate can leave one supplier in excellent condition and be damaged during the next manufacturing step.
This makes shared inspection criteria and traceability particularly important.
Critical information can include:
material lot,
glass composition,
substrate thickness,
TGV process,
dicing process,
edge inspection,
metallization batch,
and thermal-history information.
These records support root-cause analysis when reliability problems occur.
18. Why Glass Is Still Attractive Despite the Reliability Challenges
The existence of microcrack and thermal-stress challenges does not reduce the long-term potential of glass substrates.
In fact, current research activity reflects the opposite.
Industry and academia are actively developing methods to manage these problems because glass offers significant advantages for future high-density packaging.
Recent research continues to investigate stress-buffer structures, polymer liners, optimized TGV geometry and package-stack design as ways of reducing glass cracking and interfacial stress.
For AI and HPC applications, the combination of:
dimensional stability,
fine wiring capability,
high TGV density,
low electrical loss,
and scalable substrate dimensions
makes glass difficult to ignore.
The challenge is to engineer the mechanical reliability required for semiconductor-scale production.
19. The Real Target Is Not Crack-Free Glass—It Is Controlled Reliability
It is unrealistic to evaluate manufacturing glass as though absolutely no microscopic defects exist anywhere.
Instead, the semiconductor industry needs controlled defect levels and validated reliability margins.
The important questions are:
How large is the defect?
Where is it located?
What stress will it experience?
Will it grow during processing?
Will it affect electrical or mechanical reliability?
Can the manufacturing process detect it consistently?
This is a fracture-mechanics problem as much as a material-quality problem.
As AI packages grow larger and TGV density increases, this way of thinking will become increasingly important.
Conclusion
Glass substrates offer a compelling path toward larger and denser semiconductor packages for AI, HBM and heterogeneous integration.
Their low electrical loss, dimensional stability and compatibility with high-density through-glass vias give them important advantages over conventional packaging materials.
But those advantages do not eliminate mechanical reliability challenges.
Microcracks created during TGV formation, edge finishing, dicing or handling can become failure origins.
Copper-filled TGVs introduce additional thermo-mechanical stress because of CTE mismatch between copper and glass. Package build-up layers can further influence warpage and edge-crack propagation. Larger substrate dimensions magnify the importance of flatness, handling and mechanical design.
For this reason, successful glass-substrate qualification should evaluate four areas together:
TGV quality, edge quality, warpage and thermal reliability.
None of these parameters should be treated independently.
For semiconductor glass suppliers and AI-packaging manufacturers, the transition from experimental glass interposers to high-volume production will depend on the ability to control microscopic damage while maintaining dimensional accuracy across increasingly large substrates.
The future of glass packaging will therefore not be determined only by how small a TGV can be drilled or how fine an RDL can be fabricated.
It will also depend on whether the complete glass structure can survive manufacturing and operation without allowing microscopic defects to become macroscopic failures.
