Silicon carbide substrate manufacturing is entering another important diameter transition.
After years of development from 100 mm and 150 mm wafers to today’s 200 mm platforms, the industry has now begun demonstrating 300 mm (12-inch) single-crystal SiC technology.
In January 2026, Wolfspeed announced that it had successfully produced a single-crystal 300 mm silicon carbide wafer, describing the development as a pathway toward future large-scale applications in power electronics, AI infrastructure and advanced semiconductor platforms.
However, increasing the wafer diameter from 200 mm to 300 mm is not simply a matter of growing a larger crystal.
The transition introduces substantially more demanding requirements for:
- crystal growth stability;
- thermal-field control;
- defect density;
- thickness uniformity;
- TTV;
- Bow and Warp;
- residual stress;
- slicing and polishing;
- wafer handling;
- and large-area metrology.
For substrate manufacturers and device companies, the real challenge is therefore not simply:
Can a 300 mm SiC wafer be grown?
The more important question is:
Can hundreds or thousands of 300 mm wafers be produced with consistent geometry and sufficiently low defect levels for semiconductor manufacturing?
From 200mm to 300mm: Why Diameter Matters
Moving to larger wafers can potentially improve manufacturing economics because more semiconductor dies can be processed during each wafer fabrication cycle.
A 300 mm wafer has approximately 2.25 times the surface area of a 200 mm wafer.
In theory, this allows significantly more devices to be fabricated per wafer.
But SiC is fundamentally more difficult to scale than conventional silicon.
Silicon wafers benefit from decades of highly mature 300 mm crystal growth, wafering, polishing and fab infrastructure.
SiC presents a different materials challenge.
Its high growth temperature, relatively slow crystal growth rate and sensitivity to thermal gradients make it much more difficult to maintain uniform crystal quality as diameter increases.
This means that wafer diameter alone does not determine manufacturing value.
A large substrate with excessive Bow, Warp, TTV or crystallographic defects may create more problems downstream than a smaller but highly consistent wafer.
1. Crystal Growth Becomes Much More Difficult
Most bulk 4H-SiC substrates used for power semiconductor applications are produced using physical vapor transport, or PVT, crystal growth.
During PVT growth, silicon carbide source material is sublimated at very high temperature and transported toward a seed crystal where the material recrystallizes.
Increasing crystal diameter changes the thermal environment significantly.
For a 300 mm boule, manufacturers must maintain highly controlled temperature distribution across a much larger growth interface.
Problems can arise from:
- radial temperature differences;
- unstable growth interfaces;
- non-uniform sublimation;
- local thermal gradients;
- residual stress;
- polytype instability;
- and defect propagation.
Even relatively small variations in the thermal field can affect crystal quality across such a large area.
Consequently, thermal-field modelling, furnace design, insulation configuration and process control become increasingly important when moving from 200 mm toward 300 mm growth.
2. TTV Becomes a More Important Wafer-Level Parameter
Total Thickness Variation (TTV) describes the difference between the maximum and minimum wafer thickness measured across the wafer.
For semiconductor processing, low TTV helps maintain consistent contact during:
- lithography;
- epitaxy;
- wafer bonding;
- grinding;
- CMP;
- and other precision processes.
As wafer diameter increases, maintaining thickness uniformity across the entire surface becomes more difficult.
A small thickness gradient that might be manageable across a 150 mm wafer can translate into substantially larger absolute variation across a 300 mm wafer.
TTV is influenced not only by crystal growth but also by subsequent manufacturing steps including:
slicing → grinding → lapping → polishing → CMP
Every stage must therefore become more tightly controlled.
This is why the transition to larger SiC wafers requires improvements not only in crystal-growth technology but across the entire wafer manufacturing chain.
3. Bow and Warp Become Critical for Equipment Compatibility
TTV describes thickness variation, while Bow and Warp describe wafer shape.
Although the parameters are related, they measure different geometric characteristics.
Bow
Bow indicates the deviation of the wafer’s median surface relative to a reference plane, commonly measured near the wafer center.
It can be positive or negative depending on the direction of curvature.
Warp
Warp describes the difference between the highest and lowest points of the wafer’s median surface relative to a reference plane.
Warp therefore represents overall wafer deformation more broadly than Bow.
For larger-diameter SiC substrates, both parameters become particularly important.
Excessive Bow or Warp can cause problems with:
- vacuum chucking;
- lithography focus;
- wafer transfer;
- epitaxial growth;
- bonding;
- backside processing;
- CMP uniformity;
- and automated handling.
The semiconductor industry’s current focus on wafer-shape stability is already evident at the 200 mm level.
In September 2026, Wolfspeed launched a new Premium 200 mm n-type SiC substrate and specifically highlighted reduced defects and improved wafer-shape stability as key contributors to higher device manufacturing yield.
This gives an important indication of where future 300 mm qualification will focus.
Diameter alone will not be sufficient.
Wafer shape consistency from wafer to wafer and lot to lot will become a major qualification metric.
4. Defect Control Becomes Harder as Wafer Area Increases
One of the most important consequences of increasing wafer diameter is simple probability.
The larger the wafer area, the greater the chance that crystal defects will intersect critical device regions.
Important SiC crystal defects include:
Micropipes
Micropipes are hollow-core crystallographic defects historically associated with SiC bulk crystal growth.
Their density has decreased dramatically as SiC growth technology has improved.
For example, Wolfspeed’s September 2026 Premium 200 mm substrate specification states a micropipe density below 0.01 cm⁻², corresponding to fewer than three micropipes per wafer under its stated measurement method.
As the industry moves toward 300 mm, controlling such defects across a much larger surface will become even more important.
Threading Screw Dislocations — TSD
TSDs propagate through the crystal along the growth direction and can affect electrical performance and epitaxial quality.
Reducing TSD density is therefore an important part of improving substrate quality.
Threading Edge Dislocations — TED
TEDs are another common crystallographic defect in SiC substrates.
Although their impact depends on device structure and operating conditions, high defect densities can influence downstream material and device characteristics.
Basal Plane Dislocations — BPD
BPDs are especially important in power-device applications because they may interact with epitaxial growth and can contribute to stacking-fault-related reliability issues.
Stacking Faults and Other Extended Defects
As device dimensions and electrical requirements become more demanding, controlling the interaction between substrate defects and epitaxial defects becomes increasingly important.
For 300 mm SiC, inspection systems will therefore need to identify not only the number of defects but also their distribution across the wafer.
5. Residual Stress Becomes More Difficult to Manage
Large SiC crystals experience complex thermal histories during growth and cooling.
When temperature gradients are not sufficiently controlled, residual stress can remain inside the crystal.
During subsequent wafer processing, this stress can contribute to:
- wafer curvature;
- Bow;
- Warp;
- cracking;
- edge damage;
- and changes in wafer shape after material removal.
The challenge becomes more significant with larger diameters because maintaining a uniform thermal field becomes increasingly difficult.
Therefore, future 300 mm manufacturing will likely require tighter integration between:
crystal growth → stress characterization → wafer orientation → slicing strategy → grinding → polishing
rather than treating each process independently.
6. Slicing a 300mm SiC Boule Is Another Challenge
Growing the crystal is only the first step.
The boule must then be converted into wafers.
SiC is an extremely hard material, which makes slicing slower and more demanding than conventional silicon.
Manufacturers must control:
- kerf loss;
- slicing-induced damage;
- wafer thickness;
- TTV;
- surface waviness;
- subsurface damage;
- edge integrity;
- and mechanical stress.
At 300 mm diameter, wafer breakage also becomes more expensive.
A single processing failure represents a significantly larger area of high-value SiC material.
This creates strong economic incentives to improve cutting efficiency and reduce material loss.
7. Grinding, Lapping and CMP Must Scale with Diameter
After slicing, SiC wafers normally undergo multiple processes to achieve the required geometry and surface quality.
Typical steps may include:
- slicing;
- edge processing;
- grinding;
- lapping;
- mechanical polishing;
- chemical mechanical polishing;
- cleaning;
- final inspection.
Each process becomes harder as wafer area increases.
For example, CMP must remove material uniformly across a 300 mm wafer while maintaining:
- low roughness;
- controlled TTV;
- low Bow and Warp;
- minimal subsurface damage;
- and consistent edge geometry.
A high-quality center region with degraded edge performance would not be sufficient for semiconductor manufacturing.
Full-wafer uniformity becomes the key requirement.
8. Metrology Must Also Move to 300mm
Manufacturing larger SiC substrates requires corresponding advances in inspection.
Important measurements may include:
| Inspection Item | Why It Matters |
|---|---|
| Diameter | Equipment and process compatibility |
| Thickness | Mechanical and process control |
| TTV | Thickness uniformity |
| Bow | Wafer curvature |
| Warp | Overall wafer deformation |
| Surface roughness | Epitaxy and device processing |
| Micropipe density | Crystal quality |
| TSD/TED/BPD | Extended defect control |
| Surface defects | Downstream processing yield |
| Edge quality | Mechanical reliability |
| Orientation / Off-axis angle | Epitaxy and device requirements |
For production qualification, manufacturers will increasingly need wafer-level defect maps and statistical lot data, rather than isolated measurements from a few points.
9. 200mm SiC Is Becoming the Bridge to 300mm
Although 300 mm SiC development has attracted considerable attention in 2026, 200 mm remains the much more important near-term production platform.
Wolfspeed commercially launched its 200 mm SiC materials portfolio in 2025 and stated in September 2026 that its 200 mm manufacturing operations had been in continuous production since 2022. Its latest Premium 200 mm substrate emphasizes lower defect density, micropipe control and wafer-shape consistency.
This is important because many of the technologies required for 300 mm are being developed and refined today on 200 mm platforms.
These include:
- larger-diameter PVT growth;
- thermal-field modelling;
- defect reduction;
- boule slicing;
- polishing;
- wafer-shape control;
- automated inspection;
- and 200 mm semiconductor-fab integration.
In this sense, 200 mm is not merely another wafer size.
It is the technological bridge between today’s mature 150 mm supply chain and future 300 mm SiC manufacturing.
10. What Should Buyers Watch as 300mm SiC Develops?
For engineers and procurement teams following the development of 300 mm SiC, headline wafer diameter should not be the only parameter to monitor.
More meaningful indicators include:
Crystal quality
- micropipe density;
- TSD;
- TED;
- BPD;
- stacking faults.
Wafer geometry
- thickness;
- TTV;
- Bow;
- Warp;
- flatness.
Surface quality
- Ra;
- scratches;
- pits;
- particles;
- subsurface damage.
Manufacturing consistency
- wafer-to-wafer variation;
- lot-to-lot variation;
- edge quality;
- orientation accuracy;
- usable area.
Commercial maturity
- sample availability;
- production capacity;
- epitaxy compatibility;
- equipment compatibility;
- qualification status.
A 300 mm wafer demonstration represents an important technical milestone, but commercial semiconductor manufacturing requires much more than demonstrating a single large crystal.
Repeatability, yield and cost will ultimately determine when 300 mm SiC becomes a practical manufacturing platform.
From Larger Diameter to Higher Quality
The transition from 200 mm to 300 mm SiC should not be viewed simply as a race toward larger wafers.
The more important transition is toward larger wafers with tighter control of defects, geometry and surface quality.
The latest developments in 2026 illustrate this clearly.
On one side, single-crystal 300 mm SiC has already been demonstrated, showing that the next diameter generation is technically possible.
On the other, commercial 200 mm suppliers are continuing to improve micropipe density, dislocation levels and wafer-shape stability rather than focusing only on diameter.
That suggests the next phase of the SiC substrate industry will increasingly be defined by four words:
diameter, defects, geometry and consistency.
For device manufacturers, these parameters will determine whether larger SiC wafers actually deliver higher yield and better manufacturing economics.
For substrate suppliers, they will define the technical barrier between producing a large SiC wafer and producing a semiconductor-grade large-diameter SiC platform.
