1. Johdanto
Double-sided polishing (DSP) is the final and most critical step in the mechanical processing of fused silica glass wafers. It is also the longest processing stage and plays a decisive role in final product quality.
During this process, common surface defects include pits, scratches, edge chipping, cracks, and complete wafer breakage. Among these, pits and scratches can often be minimized or even repaired through process optimization and environmental control. However, edge chipping, cracks, and breakage are irreversible defects that lead directly to wafer rejection.
For ultra-thin fused silica wafers, fracture-related defects remain the primary challenge in achieving high yield and stable production.
2. Types of Fracture Defects
Fracture defects in glass wafers generally include three categories:
- Edge chipping (edge breakage)
Typically defined as visible edge damage or missing fragments longer than 0.3 mm. - Crack propagation
Cracks often initiate from chipped edges and gradually extend into the wafer body. - Complete fracture (breakage)
Once cracks propagate under stress during further processing or handling, catastrophic wafer failure occurs.
In industrial practice, once edge chipping is detected, the wafer is usually classified as a defective product and removed from further processing, as it has a high risk of failure in subsequent steps.
3. Origin of Fracture During Double-Sided Polishing
During DSP, the wafer undergoes a complex motion state driven by:
- Upper plate rotation
- Lower plate rotation
- Sun gear rotation
- Carrier (planet wheel) motion
Under these conditions, the wafer experiences a combined motion of revolution and self-rotation, making precise stress analysis highly complex.
However, production statistics show a clear trend: fracture defects almost always initiate at the wafer edge. This indicates that the edge strength of the wafer is the dominant factor governing fracture behavior.
4. Edge Strength as the Key Failure Factor
The fracture resistance of a fused silica wafer is primarily determined by its edge strength.
To improve mechanical stability, wafers are typically subjected to edge chamfering (beveling), which helps reduce stress concentration at the edges. A properly designed chamfer significantly improves fracture resistance.
However, even with edge protection, improper processing parameters or excessive mechanical load can still lead to failure initiation at the chamfered region.
5. Stress Analysis at the Wafer Edge
During DSP, the wafer edge is subjected to a combination of forces:
- F₁: Vertical pressure force
Mainly generated by the polishing pressure from the upper plate. - F₂: Horizontal force
Mainly caused by centrifugal effects during rotation and the reaction force from the carrier system.
At the chamfered edge, these forces can be decomposed into:
- Normal forces perpendicular to the chamfer surface
- Tangential forces parallel to the chamfer surface
The combined stress state can be expressed as the superposition of:
- Normal stress (compressive/tensile components)
- Shear stress (sliding components)
When these stresses exceed the mechanical strength limit of fused silica, crack initiation occurs, typically starting at the edge and propagating inward.
6. Failure Mechanism in Ultra-Thin Wafers
For ultra-thin fused silica wafers (typically thickness < 0.3 mm), fracture risk increases significantly due to several factors:
6.1 Reduced Structural Strength
As thickness decreases, the overall mechanical rigidity of the wafer is significantly reduced, making it more sensitive to external stress.
6.2 Reduced Chamfer Protection Area
Ultra-thin wafers have a much smaller chamfer volume and contact area. As a result, the protective effect of edge beveling is weakened.
6.3 Increased Stress Concentration
Under the same polishing conditions:
- Contact area decreases
- Local stress per unit area increases
- Edge stress concentration becomes significantly higher
This leads to a rapid increase in both normal and shear stress at the edge.
7. Päätelmät
Fracture defects in fused silica glass wafers during double-sided polishing are primarily caused by excessive stress at the wafer edge. When the combined normal and shear stresses exceed the mechanical strength limit of the material, edge chipping, crack propagation, and final breakage occur.
Ultra-thin wafers are particularly vulnerable due to reduced thickness, weakened edge protection, and increased stress concentration.
Therefore, improving wafer yield requires a strong focus on:
- Edge strength optimization
- Chamfer design improvement
- Polishing pressure control
- Rotation speed optimization
- Process stability enhancement
By carefully controlling these factors, fracture risk can be significantly reduced, leading to higher yield and improved manufacturing reliability in fused silica wafer production.
